Home
last modified time | relevance | path

Searched refs:mmUVD_STATUS (Results 1 – 15 of 15) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v4_2_hw_fini()
265 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
319 status = RREG32(mmUVD_STATUS); in uvd_v4_2_start()
345 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start()
390 status = RREG32(mmUVD_STATUS); in uvd_v4_2_stop()
433 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
Dvcn_v2_5.c310 if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) in vcn_v2_5_hw_fini()
727 tmp = RREG32_SOC15(UVD, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_5_start()
728 WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp); in vcn_v2_5_start()
807 status = RREG32_SOC15(UVD, i, mmUVD_STATUS); in vcn_v2_5_start()
842 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0, in vcn_v2_5_start()
901 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r); in vcn_v2_5_stop()
939 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v2_5_stop()
1260 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle()
1274 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle()
Duvd_v5_0.c213 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini()
364 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
390 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
452 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
Dvcn_v1_0.c237 RREG32_SOC15(VCN, 0, mmUVD_STATUS)) in vcn_v1_0_hw_fini()
794 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
795 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
866 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start_spg_mode()
900 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
901 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
1143 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code); in vcn_v1_0_stop_spg_mode()
1173 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); in vcn_v1_0_stop_spg_mode()
1356 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle()
1364 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle()
Dvcn_v2_0.c298 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
1074 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_0_start()
1075 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v2_0_start()
1149 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v2_0_start()
1180 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, in vcn_v2_0_start()
1276 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r); in vcn_v2_0_stop()
1319 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); in vcn_v2_0_stop()
1397 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle()
1405 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle()
Duvd_v6_0.c540 if (RREG32(mmUVD_STATUS) != 0) in uvd_v6_0_hw_fini()
781 status = RREG32(mmUVD_STATUS); in uvd_v6_0_start()
808 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in uvd_v6_0_start()
885 WREG32(mmUVD_STATUS, 0); in uvd_v6_0_stop()
1141 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK)) in uvd_v6_0_check_soft_reset()
Duvd_v7_0.c800 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
890 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
912 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); in uvd_v7_0_sriov_start()
1027 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); in uvd_v7_0_start()
1057 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, in uvd_v7_0_start()
1462 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h84 #define mmUVD_STATUS 0x3DAF macro
Duvd_4_2_d.h76 #define mmUVD_STATUS 0x3daf macro
Duvd_5_0_d.h82 #define mmUVD_STATUS 0x3daf macro
Duvd_6_0_d.h98 #define mmUVD_STATUS 0x3daf macro
Duvd_7_0_offset.h206 #define mmUVD_STATUS … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h394 #define mmUVD_STATUS … macro
Dvcn_2_5_offset.h475 #define mmUVD_STATUS … macro
Dvcn_2_0_0_offset.h698 #define mmUVD_STATUS … macro