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Searched refs:mmUVD_SOFT_RESET (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c308 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v4_2_start()
310 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v4_2_start()
312 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
329 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start()
332 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
429 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v4_2_stop()
Duvd_v5_0.c317 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v5_0_start()
348 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
358 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v5_0_start()
374 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start()
377 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
443 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_stop()
Duvd_v7_0.c857 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
877 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
906 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); in uvd_v7_0_sriov_start()
971 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, in uvd_v7_0_start()
1007 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, in uvd_v7_0_start()
1020 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); in uvd_v7_0_start()
1037 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), in uvd_v7_0_start()
1041 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, in uvd_v7_0_start()
1134 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, in uvd_v7_0_stop()
Dvcn_v2_0.c1003 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); in vcn_v2_0_start_dpg_mode()
1125 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v2_0_start()
1132 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); in vcn_v2_0_start()
1135 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); in vcn_v2_0_start()
1159 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_start()
1163 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v2_0_start()
1304 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
1309 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
1314 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
Dvcn_v1_0.c850 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode()
857 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); in vcn_v1_0_start_spg_mode()
860 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); in vcn_v1_0_start_spg_mode()
876 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_start_spg_mode()
880 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode()
1044 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
1152 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
1165 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
1169 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
Duvd_v6_0.c724 WREG32(mmUVD_SOFT_RESET, in uvd_v6_0_start()
764 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v6_0_start()
774 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v6_0_start()
876 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v6_0_stop()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h83 #define mmUVD_SOFT_RESET 0x3DA0 macro
Duvd_4_2_d.h67 #define mmUVD_SOFT_RESET 0x3da0 macro
Duvd_5_0_d.h73 #define mmUVD_SOFT_RESET 0x3da0 macro
Duvd_6_0_d.h89 #define mmUVD_SOFT_RESET 0x3da0 macro
Duvd_7_0_offset.h190 #define mmUVD_SOFT_RESET … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h378 #define mmUVD_SOFT_RESET … macro
Dvcn_2_5_offset.h479 #define mmUVD_SOFT_RESET … macro
Dvcn_2_0_0_offset.h672 #define mmUVD_SOFT_RESET … macro