Searched refs:mmUVD_SEMA_CNTL (Results 1 – 12 of 12) sorted by relevance
78 #define mmUVD_SEMA_CNTL 0x3D00 macro
38 #define mmUVD_SEMA_CNTL 0x3d00 macro
44 #define mmUVD_SEMA_CNTL 0x3d00 macro
55 #define mmUVD_SEMA_CNTL 0x3d00 macro
122 #define mmUVD_SEMA_CNTL … macro
248 #define mmUVD_SEMA_CNTL … macro
803 #define mmUVD_SEMA_CNTL … macro
476 #define mmUVD_SEMA_CNTL … macro
191 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
188 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
503 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
571 mmUVD_SEMA_CNTL), 0)); in uvd_v7_0_hw_init()
