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Searched refs:mmUVD_RB_WPTR2 (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h43 #define mmUVD_RB_WPTR2 0x3c25 macro
Duvd_7_0_offset.h92 #define mmUVD_RB_WPTR2 … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h214 #define mmUVD_RB_WPTR2 … macro
Dvcn_2_5_offset.h557 #define mmUVD_RB_WPTR2 … macro
Dvcn_2_0_0_offset.h926 #define mmUVD_RB_WPTR2 … macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c1216 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1240 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v2_0_stop_dpg_mode()
1373 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1686 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v2_0_enc_ring_get_wptr()
1713 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
Dvcn_v1_0.c946 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1194 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v1_0_stop_dpg_mode()
1272 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1621 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v1_0_enc_ring_get_wptr()
1639 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, in vcn_v1_0_enc_ring_set_wptr()
Duvd_v6_0.c128 return RREG32(mmUVD_RB_WPTR2); in uvd_v6_0_enc_ring_get_wptr()
160 WREG32(mmUVD_RB_WPTR2, in uvd_v6_0_enc_ring_set_wptr()
850 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
Dvcn_v2_5.c878 WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1069 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); in vcn_v2_5_enc_ring_get_wptr()
1096 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
Duvd_v7_0.c126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); in uvd_v7_0_enc_ring_get_wptr()
165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, in uvd_v7_0_enc_ring_set_wptr()
1102 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in uvd_v7_0_start()