Searched refs:mmUVD_RB_RPTR2 (Results 1 – 10 of 10) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_6_0_d.h | 42 #define mmUVD_RB_RPTR2 0x3c24 macro
|
| D | uvd_7_0_offset.h | 90 #define mmUVD_RB_RPTR2 … macro
|
| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 212 #define mmUVD_RB_RPTR2 … macro
|
| D | vcn_2_5_offset.h | 555 #define mmUVD_RB_RPTR2 … macro
|
| D | vcn_2_0_0_offset.h | 924 #define mmUVD_RB_RPTR2 … macro
|
| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_0.c | 1215 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1241 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); in vcn_v2_0_stop_dpg_mode()
1372 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1663 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); in vcn_v2_0_enc_ring_get_rptr()
|
| D | vcn_v1_0.c | 945 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1195 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); in vcn_v1_0_stop_dpg_mode()
1271 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1604 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); in vcn_v1_0_enc_ring_get_rptr()
|
| D | uvd_v6_0.c | 98 return RREG32(mmUVD_RB_RPTR2); in uvd_v6_0_enc_ring_get_rptr()
849 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
|
| D | vcn_v2_5.c | 877 WREG32_SOC15(UVD, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1046 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); in vcn_v2_5_enc_ring_get_rptr()
|
| D | uvd_v7_0.c | 92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); in uvd_v7_0_enc_ring_get_rptr()
1101 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in uvd_v7_0_start()
|
