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Searched refs:mmUVD_RB_RPTR (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h47 #define mmUVD_RB_RPTR 0x3c29 macro
Duvd_7_0_offset.h100 #define mmUVD_RB_RPTR … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h222 #define mmUVD_RB_RPTR … macro
Dvcn_2_5_offset.h545 #define mmUVD_RB_RPTR … macro
Dvcn_2_0_0_offset.h934 #define mmUVD_RB_RPTR … macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c1208 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1238 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); in vcn_v2_0_stop_dpg_mode()
1365 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1661 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); in vcn_v2_0_enc_ring_get_rptr()
Dvcn_v1_0.c938 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1192 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); in vcn_v1_0_stop_dpg_mode()
1264 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1602 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); in vcn_v1_0_enc_ring_get_rptr()
Duvd_v6_0.c96 return RREG32(mmUVD_RB_RPTR); in uvd_v6_0_enc_ring_get_rptr()
842 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
Dvcn_v2_5.c870 WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1044 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); in vcn_v2_5_enc_ring_get_rptr()
Duvd_v7_0.c90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); in uvd_v7_0_enc_ring_get_rptr()
1094 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_start()