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Searched refs:mmUVD_RB_BASE_LO2 (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h39 #define mmUVD_RB_BASE_LO2 0x3c21 macro
Duvd_7_0_offset.h84 #define mmUVD_RB_BASE_LO2 … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h206 #define mmUVD_RB_BASE_LO2 … macro
Dvcn_2_5_offset.h549 #define mmUVD_RB_BASE_LO2 … macro
Dvcn_2_0_0_offset.h918 #define mmUVD_RB_BASE_LO2 … macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c1217 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_start()
1369 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
Dvcn_v1_0.c947 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
1268 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
Duvd_v6_0.c851 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr); in uvd_v6_0_start()
Dvcn_v2_5.c879 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_start()
Duvd_v7_0.c1103 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); in uvd_v7_0_start()