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Searched refs:mmUVD_RB_BASE_LO (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h44 #define mmUVD_RB_BASE_LO 0x3c26 macro
Duvd_7_0_offset.h94 #define mmUVD_RB_BASE_LO … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h216 #define mmUVD_RB_BASE_LO … macro
Dvcn_2_5_offset.h539 #define mmUVD_RB_BASE_LO … macro
Dvcn_2_0_0_offset.h928 #define mmUVD_RB_BASE_LO … macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Duvd_v7_0.c901 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); in uvd_v7_0_sriov_start()
1096 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); in uvd_v7_0_start()
Dvcn_v2_0.c1210 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_start()
1362 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
Dvcn_v1_0.c940 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
1261 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
Duvd_v6_0.c844 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr); in uvd_v6_0_start()
Dvcn_v2_5.c872 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_start()