Home
last modified time | relevance | path

Searched refs:mmUVD_RB_BASE_HI (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h45 #define mmUVD_RB_BASE_HI 0x3c27 macro
Duvd_7_0_offset.h96 #define mmUVD_RB_BASE_HI … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h218 #define mmUVD_RB_BASE_HI … macro
Dvcn_2_5_offset.h541 #define mmUVD_RB_BASE_HI … macro
Dvcn_2_0_0_offset.h930 #define mmUVD_RB_BASE_HI … macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Duvd_v7_0.c902 …MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_ad… in uvd_v7_0_sriov_start()
1097 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
Dvcn_v2_0.c1211 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1363 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
Dvcn_v1_0.c941 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1262 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
Duvd_v6_0.c845 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
Dvcn_v2_5.c873 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()