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Searched refs:mmUVD_MPC_SET_MUXA1_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_offset.h167 #define mmUVD_MPC_SET_MUXA1_BASE_IDX … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h349 #define mmUVD_MPC_SET_MUXA1_BASE_IDX … macro
Dvcn_2_5_offset.h752 #define mmUVD_MPC_SET_MUXA1_BASE_IDX … macro
Dvcn_2_0_0_offset.h599 #define mmUVD_MPC_SET_MUXA1_BASE_IDX … macro