Searched refs:mmUVD_MPC_SET_MUXA0 (Results 1 – 15 of 15) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 56 #define mmUVD_MPC_SET_MUXA0 0x3D79 macro
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| D | uvd_4_2_d.h | 54 #define mmUVD_MPC_SET_MUXA0 0x3d79 macro
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| D | uvd_5_0_d.h | 60 #define mmUVD_MPC_SET_MUXA0 0x3d79 macro
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| D | uvd_6_0_d.h | 76 #define mmUVD_MPC_SET_MUXA0 0x3d79 macro
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| D | uvd_7_0_offset.h | 164 #define mmUVD_MPC_SET_MUXA0 … macro
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 346 #define mmUVD_MPC_SET_MUXA0 … macro
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| D | vcn_2_5_offset.h | 749 #define mmUVD_MPC_SET_MUXA0 … macro
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| D | vcn_2_0_0_offset.h | 596 #define mmUVD_MPC_SET_MUXA0 … macro
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| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v4_2.c | 293 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v4_2_start()
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| D | uvd_v5_0.c | 340 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v5_0_start()
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| D | vcn_v2_0.c | 975 UVD, 0, mmUVD_MPC_SET_MUXA0), in vcn_v2_0_start_dpg_mode()
1103 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, in vcn_v2_0_start()
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| D | vcn_v1_0.c | 823 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, in vcn_v1_0_start_spg_mode()
1021 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, in vcn_v1_0_start_dpg_mode()
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| D | uvd_v6_0.c | 756 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v6_0_start()
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| D | vcn_v2_5.c | 761 WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXA0, in vcn_v2_5_start()
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| D | uvd_v7_0.c | 999 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v7_0_start()
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