Home
last modified time | relevance | path

Searched refs:mmUVD_MASTINT_EN (Results 1 – 15 of 15) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h52 #define mmUVD_MASTINT_EN 0x3D40 macro
Duvd_4_2_d.h47 #define mmUVD_MASTINT_EN 0x3d40 macro
Duvd_5_0_d.h53 #define mmUVD_MASTINT_EN 0x3d40 macro
Duvd_6_0_d.h69 #define mmUVD_MASTINT_EN 0x3d40 macro
Duvd_7_0_offset.h152 #define mmUVD_MASTINT_EN macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c278 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start()
343 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v4_2_start()
Duvd_v5_0.c310 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start()
387 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start()
Duvd_v7_0.c848 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
885 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
961 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, in uvd_v7_0_start()
1052 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), in uvd_v7_0_start()
Dvcn_v2_0.c956 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_0_start_dpg_mode()
1012 UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_0_start_dpg_mode()
1085 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v2_0_start()
1175 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_0_start()
Dvcn_v1_0.c801 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v1_0_start_spg_mode()
891 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v1_0_start_spg_mode()
998 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, in vcn_v1_0_start_dpg_mode()
1052 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, in vcn_v1_0_start_dpg_mode()
Dvcn_v2_5.c742 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
837 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in vcn_v2_5_start()
Duvd_v6_0.c803 WREG32_P(mmUVD_MASTINT_EN, in uvd_v6_0_start()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h330 #define mmUVD_MASTINT_EN macro
Dvcn_2_5_offset.h521 #define mmUVD_MASTINT_EN macro
Dvcn_2_0_0_offset.h538 #define mmUVD_MASTINT_EN macro