| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 48 #define mmUVD_LMI_CTRL2 0x3D3D macro
|
| D | uvd_4_2_d.h | 46 #define mmUVD_LMI_CTRL2 0x3d3d macro
|
| D | uvd_5_0_d.h | 52 #define mmUVD_LMI_CTRL2 0x3d3d macro
|
| D | uvd_6_0_d.h | 68 #define mmUVD_LMI_CTRL2 0x3d3d macro
|
| D | uvd_7_0_offset.h | 150 #define mmUVD_LMI_CTRL2 … macro
|
| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v5_0.c | 313 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start()
355 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start()
439 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_stop()
450 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_stop()
|
| D | uvd_v7_0.c | 852 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_sriov_start()
909 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_sriov_start()
965 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), in uvd_v7_0_start()
1016 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, in uvd_v7_0_start()
1128 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_stop()
1142 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, in uvd_v7_0_stop()
|
| D | uvd_v4_2.c | 306 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start()
411 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v4_2_stop()
|
| D | vcn_v2_5.c | 793 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
914 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v2_5_stop()
916 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v2_5_stop()
|
| D | vcn_v2_0.c | 1007 UVD, 0, mmUVD_LMI_CTRL2), in vcn_v2_0_start_dpg_mode()
1129 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v2_0_start()
1289 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); in vcn_v2_0_stop()
1291 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); in vcn_v2_0_stop()
|
| D | uvd_v6_0.c | 872 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v6_0_stop()
883 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v6_0_stop()
|
| D | vcn_v1_0.c | 854 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v1_0_start_spg_mode()
1047 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, in vcn_v1_0_start_dpg_mode()
|
| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 328 #define mmUVD_LMI_CTRL2 … macro
|
| D | vcn_2_5_offset.h | 943 #define mmUVD_LMI_CTRL2 … macro
|
| D | vcn_2_0_0_offset.h | 536 #define mmUVD_LMI_CTRL2 … macro
|
