Home
last modified time | relevance | path

Searched refs:mmUVD_JRBC_RB_CNTL (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c953 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | in vcn_v1_0_start_spg_mode()
959 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); in vcn_v1_0_start_spg_mode()
1322 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, in vcn_v1_0_pause_dpg_mode()
1331 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, in vcn_v1_0_pause_dpg_mode()
2052 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); in vcn_v1_0_jpeg_ring_set_patch_ring()
2064 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); in vcn_v1_0_jpeg_ring_set_patch_ring()
2097 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); in vcn_v1_0_jpeg_ring_set_patch_ring()
Dvcn_v2_5.c662 WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v2_5_start()
669 WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v2_5_start()
Dvcn_v2_0.c714 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v2_0_start()
721 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v2_0_start()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h264 #define mmUVD_JRBC_RB_CNTL … macro
Dvcn_2_5_offset.h127 #define mmUVD_JRBC_RB_CNTL … macro
Dvcn_2_0_0_offset.h124 #define mmUVD_JRBC_RB_CNTL … macro