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Searched refs:mmUVD_GPCOM_VCPU_DATA1 (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h44 #define mmUVD_GPCOM_VCPU_DATA1 0x3BC5 macro
Duvd_4_2_d.h32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 macro
Duvd_5_0_d.h32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 macro
Duvd_6_0_d.h32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 macro
Duvd_7_0_offset.h58 #define mmUVD_GPCOM_VCPU_DATA1 … macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c905 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
912 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
1036 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_wreg()
1049 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_vm_flush()
1064 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
Duvd_v4_2.c455 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v4_2_ring_emit_fence()
462 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v4_2_ring_emit_fence()
Duvd_v5_0.c472 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v5_0_ring_emit_fence()
479 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v5_0_ring_emit_fence()
Dvcn_v1_0.c138 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v1_0_sw_init()
1491 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_fence()
1501 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_fence()
1549 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_reg_wait()
1583 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_wreg()
Duvd_v7_0.c1169 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1179 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1344 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_wreg()
1360 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_reg_wait()
Damdgpu_uvd.c909 case mmUVD_GPCOM_VCPU_DATA1: in amdgpu_uvd_cs_reg()
Dvcn_v2_5.c180 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
Dvcn_v2_0.c181 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_0_sw_init()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h142 #define mmUVD_GPCOM_VCPU_DATA1 … macro
Dvcn_2_5_offset.h503 #define mmUVD_GPCOM_VCPU_DATA1 … macro
Dvcn_2_0_0_offset.h814 #define mmUVD_GPCOM_VCPU_DATA1 … macro