| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v5_0.c | 652 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
691 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating()
746 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
749 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
755 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
758 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
823 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_get_clockgating_state()
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| D | uvd_v4_2.c | 586 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
589 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
595 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
598 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
609 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_set_dcm()
625 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v4_2_set_dcm()
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| D | vcn_v2_5.c | 440 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
447 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
475 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
496 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
558 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
565 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
567 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
587 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
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| D | uvd_v6_0.c | 1307 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1347 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_set_sw_clock_gating()
1404 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1407 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1413 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1416 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1486 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_get_clockgating_state()
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| D | vcn_v2_0.c | 514 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
521 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
546 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
567 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
644 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
795 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
802 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
804 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
825 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
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| D | vcn_v1_0.c | 462 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
470 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
495 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
516 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
587 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
594 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
596 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
617 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
675 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
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| D | uvd_v7_0.c | 844 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), in uvd_v7_0_sriov_start()
957 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start()
1585 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1631 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 34 #define mmUVD_CGC_CTRL 0x3D2C macro
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| D | uvd_4_2_d.h | 44 #define mmUVD_CGC_CTRL 0x3d2c macro
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| D | uvd_5_0_d.h | 50 #define mmUVD_CGC_CTRL 0x3d2c macro
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| D | uvd_6_0_d.h | 66 #define mmUVD_CGC_CTRL 0x3d2c macro
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| D | uvd_7_0_offset.h | 146 #define mmUVD_CGC_CTRL … macro
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 308 #define mmUVD_CGC_CTRL … macro
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| D | vcn_2_5_offset.h | 489 #define mmUVD_CGC_CTRL … macro
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| D | vcn_2_0_0_offset.h | 508 #define mmUVD_CGC_CTRL … macro
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