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Searched refs:mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h655 #define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX … macro
Dgc_9_2_1_offset.h627 #define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX … macro
Dgc_9_1_offset.h649 #define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX … macro