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Searched refs:mmSDMA0_PHASE1_QUANTUM (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h102 #define mmSDMA0_PHASE1_QUANTUM … macro
Dsdma0_4_0_offset.h104 #define mmSDMA0_PHASE1_QUANTUM 0x002d macro
Dsdma0_4_2_2_offset.h104 #define mmSDMA0_PHASE1_QUANTUM … macro
Dsdma0_4_2_offset.h104 #define mmSDMA0_PHASE1_QUANTUM … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h177 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
Doss_3_0_1_d.h175 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
Doss_2_0_d.h240 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
Doss_3_0_d.h312 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c384 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], in cik_ctx_switch_enable()
Dsdma_v3_0.c595 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable()
Dsdma_v5_0.c559 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_0_ctx_switch_enable()
Dsdma_v4_0.c922 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); in sdma_v4_0_ctx_switch_enable()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h76 #define mmSDMA0_PHASE1_QUANTUM … macro