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Searched refs:mmSDMA0_PHASE0_QUANTUM (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h100 #define mmSDMA0_PHASE0_QUANTUM … macro
Dsdma0_4_0_offset.h102 #define mmSDMA0_PHASE0_QUANTUM 0x002c macro
Dsdma0_4_2_2_offset.h102 #define mmSDMA0_PHASE0_QUANTUM … macro
Dsdma0_4_2_offset.h102 #define mmSDMA0_PHASE0_QUANTUM … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h176 #define mmSDMA0_PHASE0_QUANTUM 0x3414 macro
Doss_3_0_1_d.h174 #define mmSDMA0_PHASE0_QUANTUM 0x3414 macro
Doss_2_0_d.h239 #define mmSDMA0_PHASE0_QUANTUM 0x3414 macro
Doss_3_0_d.h311 #define mmSDMA0_PHASE0_QUANTUM 0x3414 macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c382 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], in cik_ctx_switch_enable()
Dsdma_v3_0.c593 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable()
Dsdma_v5_0.c557 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_0_ctx_switch_enable()
Dsdma_v4_0.c921 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); in sdma_v4_0_ctx_switch_enable()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h74 #define mmSDMA0_PHASE0_QUANTUM … macro