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Searched refs:mmSDMA0_GFX_RB_WPTR (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dsdma_v2_4.c210 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; in sdma_v2_4_ring_get_wptr()
226 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_ring_set_wptr()
450 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
466 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_gfx_resume()
Dcik_sdma.c183 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; in cik_sdma_ring_get_wptr()
197 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], in cik_sdma_ring_set_wptr()
472 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
488 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in cik_sdma_gfx_resume()
Dsdma_v5_0.c302 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; in sdma_v5_0_ring_get_wptr()
349 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), in sdma_v5_0_ring_set_wptr()
635 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_0_gfx_resume()
669 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); in sdma_v5_0_gfx_resume()
Dsdma_v3_0.c372 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; in sdma_v3_0_ring_get_wptr()
399 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
725 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
Dsdma_v4_0.c571 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); in sdma_v4_0_ring_get_wptr()
614 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, in sdma_v4_0_ring_set_wptr()
1001 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); in sdma_v4_0_gfx_resume()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h214 #define mmSDMA0_GFX_RB_WPTR … macro
Dsdma0_4_0_offset.h218 #define mmSDMA0_GFX_RB_WPTR 0x0085 macro
Dsdma0_4_2_2_offset.h218 #define mmSDMA0_GFX_RB_WPTR … macro
Dsdma0_4_2_offset.h214 #define mmSDMA0_GFX_RB_WPTR … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h191 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
Doss_3_0_1_d.h218 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
Doss_2_0_d.h250 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
Doss_3_0_d.h343 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h209 #define mmSDMA0_GFX_RB_WPTR … macro