| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v3_0.c | 83 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
96 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
114 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
121 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
135 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
149 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
164 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
178 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
1448 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); in sdma_v3_0_update_sdma_medium_grain_clock_gating()
1458 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); in sdma_v3_0_update_sdma_medium_grain_clock_gating()
[all …]
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| D | mxgpu_vi.c | 92 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
223 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
244 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
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| D | cik_sdma.c | 888 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
889 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
891 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
894 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
896 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
899 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
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| D | sdma_v4_0.c | 88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
249 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
2118 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); in sdma_v4_0_update_medium_grain_clock_gating()
2128 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); in sdma_v4_0_update_medium_grain_clock_gating()
2132 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); in sdma_v4_0_update_medium_grain_clock_gating()
2142 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); in sdma_v4_0_update_medium_grain_clock_gating()
2226 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_get_clockgating_state()
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| D | sdma_v5_0.c | 1465 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); in sdma_v5_0_update_medium_grain_clock_gating()
1475 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); in sdma_v5_0_update_medium_grain_clock_gating()
1478 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); in sdma_v5_0_update_medium_grain_clock_gating()
1488 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); in sdma_v5_0_update_medium_grain_clock_gating()
1557 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); in sdma_v5_0_get_clockgating_state()
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| D | sdma_v2_4.c | 69 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
76 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| D | sdma0_4_1_offset.h | 66 #define mmSDMA0_CLK_CTRL … macro
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| D | sdma0_4_0_offset.h | 68 #define mmSDMA0_CLK_CTRL 0x001b macro
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| D | sdma0_4_2_2_offset.h | 68 #define mmSDMA0_CLK_CTRL … macro
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| D | sdma0_4_2_offset.h | 68 #define mmSDMA0_CLK_CTRL … macro
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_2_4_d.h | 160 #define mmSDMA0_CLK_CTRL 0x3403 macro
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| D | oss_3_0_1_d.h | 157 #define mmSDMA0_CLK_CTRL 0x3403 macro
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| D | oss_2_0_d.h | 222 #define mmSDMA0_CLK_CTRL 0x3403 macro
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| D | oss_3_0_d.h | 294 #define mmSDMA0_CLK_CTRL 0x3403 macro
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_10_1_0_offset.h | 40 #define mmSDMA0_CLK_CTRL … macro
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