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Searched refs:mmRLC_SRM_INDEX_CNTL_ADDR_0 (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c698 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
699 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
700 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
701 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
702 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
703 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
704 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
705 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
2739 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) in gfx_v9_1_init_rlc_save_restore_list()
Dgfx_v8_0.c4029 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0; in gfx_v8_0_init_save_restore_list()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_1_d.h1459 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b macro
Dgfx_8_0_d.h1463 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6132 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 … macro
Dgc_9_1_offset.h6376 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 … macro
Dgc_9_2_1_offset.h6352 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 … macro
Dgc_10_1_0_offset.h9462 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 … macro