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Searched refs:mmRLC_SRM_CNTL (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/inc/
Dpolaris10_pwrvirus.h50 { 0x00000002, mmRLC_SRM_CNTL },
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_1_d.h1448 #define mmRLC_SRM_CNTL 0xec80 macro
Dgfx_8_0_d.h1452 #define mmRLC_SRM_CNTL 0xec80 macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c1865 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); in gfx_v10_0_rlc_enable_srm()
1868 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); in gfx_v10_0_rlc_enable_srm()
Dgfx_v9_0.c2680 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); in gfx_v9_1_init_rlc_save_restore_list()
2682 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); in gfx_v9_1_init_rlc_save_restore_list()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6114 #define mmRLC_SRM_CNTL macro
Dgc_9_1_offset.h6358 #define mmRLC_SRM_CNTL macro
Dgc_9_2_1_offset.h6334 #define mmRLC_SRM_CNTL macro
Dgc_10_1_0_offset.h9452 #define mmRLC_SRM_CNTL macro