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Searched refs:mmRLC_PG_CNTL (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c3721 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3727 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3735 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3741 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3748 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_cp_pg()
3754 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_cp_pg()
3761 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gds_pg()
3767 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gds_pg()
3784 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3787 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_cgpg()
[all …]
Dgfx_v9_0.c2832 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2837 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2846 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2851 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2860 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_cp_power_gating()
2865 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_cp_power_gating()
2873 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_cg_power_gating()
2878 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_cg_power_gating()
2886 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_pipeline_powergating()
2891 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_pipeline_powergating()
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Dgfx_v6_0.c2691 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_cp_pg()
2697 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_cp_pg()
2801 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_gfx_static_mgpg()
2807 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_gfx_static_mgpg()
2815 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_gfx_dynamic_mgpg()
2821 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_gfx_dynamic_mgpg()
Dgfx_v10_0.c1832 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); in gfx_v10_0_rlc_smu_handshake_cntl()
1846 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); in gfx_v10_0_rlc_smu_handshake_cntl()
1922 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); in gfx_v10_0_rlc_resume()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1165 #define mmRLC_PG_CNTL 0x30D7 macro
Dgfx_7_0_d.h1275 #define mmRLC_PG_CNTL 0x3103 macro
Dgfx_7_2_d.h1288 #define mmRLC_PG_CNTL 0x3103 macro
Dgfx_8_1_d.h1388 #define mmRLC_PG_CNTL 0xec43 macro
Dgfx_8_0_d.h1386 #define mmRLC_PG_CNTL 0xec43 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6010 #define mmRLC_PG_CNTL … macro
Dgc_9_1_offset.h6254 #define mmRLC_PG_CNTL … macro
Dgc_9_2_1_offset.h6230 #define mmRLC_PG_CNTL … macro
Dgc_10_1_0_offset.h9354 #define mmRLC_PG_CNTL … macro