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Searched refs:mmRLC_MEM_SLP_CNTL (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1156 #define mmRLC_MEM_SLP_CNTL 0x30D8 macro
Dgfx_7_0_d.h1247 #define mmRLC_MEM_SLP_CNTL 0x30c6 macro
Dgfx_7_2_d.h1260 #define mmRLC_MEM_SLP_CNTL 0x30c6 macro
Dgfx_8_1_d.h1351 #define mmRLC_MEM_SLP_CNTL 0xec06 macro
Dgfx_8_0_d.h1349 #define mmRLC_MEM_SLP_CNTL 0xec06 macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c4065 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
4068 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
4089 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
4092 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
4299 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_get_clockgating_state()
Dgfx_v9_0.c4644 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4647 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4673 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4676 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4931 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_get_clockgating_state()
Dgfx_v8_0.c708 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5515 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v8_0_get_clockgating_state()
5711 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v8_0_update_medium_grain_clock_gating()
5714 WREG32(mmRLC_MEM_SLP_CNTL, data); in gfx_v8_0_update_medium_grain_clock_gating()
Dgfx_v7_0.c3670 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3673 WREG32(mmRLC_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h5942 #define mmRLC_MEM_SLP_CNTL macro
Dgc_9_1_offset.h6186 #define mmRLC_MEM_SLP_CNTL macro
Dgc_9_2_1_offset.h6150 #define mmRLC_MEM_SLP_CNTL macro
Dgc_10_1_0_offset.h9276 #define mmRLC_MEM_SLP_CNTL macro