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Searched refs:mmRLC_CNTL (Results 1 – 15 of 15) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/inc/
Dpolaris10_pwrvirus.h49 { 0x00000000, mmRLC_CNTL },
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2461 tmp = RREG32(mmRLC_CNTL); in gfx_v6_0_update_rlc()
2463 WREG32(mmRLC_CNTL, rlc); in gfx_v6_0_update_rlc()
2470 orig = data = RREG32(mmRLC_CNTL); in gfx_v6_0_halt_rlc()
2474 WREG32(mmRLC_CNTL, data); in gfx_v6_0_halt_rlc()
2484 WREG32(mmRLC_CNTL, 0); in gfx_v6_0_rlc_stop()
2492 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v6_0_rlc_start()
Dgfx_v7_0.c3398 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc()
3400 WREG32(mmRLC_CNTL, rlc); in gfx_v7_0_update_rlc()
3407 orig = data = RREG32(mmRLC_CNTL); in gfx_v7_0_halt_rlc()
3413 WREG32(mmRLC_CNTL, data); in gfx_v7_0_halt_rlc()
3471 WREG32(mmRLC_CNTL, 0); in gfx_v7_0_rlc_stop()
3487 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v7_0_rlc_start()
Dgfx_v10_0.c1813 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_stop()
1816 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); in gfx_v10_0_rlc_stop()
2203 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_backdoor_autoload_enable()
4013 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_is_rlc_enabled()
Dgfx_v8_0.c5577 rlc_setting = RREG32(mmRLC_CNTL); in gfx_v8_0_is_rlc_enabled()
5588 data = RREG32(mmRLC_CNTL); in gfx_v8_0_set_safe_mode()
5616 data = RREG32(mmRLC_CNTL); in gfx_v8_0_unset_safe_mode()
Dgfx_v9_0.c4544 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v9_0_is_rlc_enabled()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1136 #define mmRLC_CNTL 0x30C0 macro
Dgfx_7_0_d.h1240 #define mmRLC_CNTL 0x30c0 macro
Dgfx_7_2_d.h1253 #define mmRLC_CNTL 0x30c0 macro
Dgfx_8_1_d.h1345 #define mmRLC_CNTL 0xec00 macro
Dgfx_8_0_d.h1342 #define mmRLC_CNTL 0xec00 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h5936 #define mmRLC_CNTL … macro
Dgc_9_1_offset.h6180 #define mmRLC_CNTL … macro
Dgc_9_2_1_offset.h6144 #define mmRLC_CNTL … macro
Dgc_10_1_0_offset.h9268 #define mmRLC_CNTL … macro