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Searched refs:mmPA_SC_ENHANCE (Results 1 – 15 of 15) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c103 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
239 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
Dgfx_v8_0.c202 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
313 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
344 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
376 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
420 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
476 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
575 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
681 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
Dsoc15.c431 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || in soc15_program_register_sequence()
Dgfx_v9_0.c507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
Dgfx_v10_0.c120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
Dgfx_v7_0.c2042 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); in gfx_v7_0_constants_init()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h967 #define mmPA_SC_ENHANCE 0x22FC macro
Dgfx_7_0_d.h1093 #define mmPA_SC_ENHANCE 0x22fc macro
Dgfx_7_2_d.h1106 #define mmPA_SC_ENHANCE 0x22fc macro
Dgfx_8_1_d.h1189 #define mmPA_SC_ENHANCE 0x22fc macro
Dgfx_8_0_d.h1188 #define mmPA_SC_ENHANCE 0x22fc macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h376 #define mmPA_SC_ENHANCE … macro
Dgc_9_1_offset.h370 #define mmPA_SC_ENHANCE … macro
Dgc_9_2_1_offset.h366 #define mmPA_SC_ENHANCE … macro
Dgc_10_1_0_offset.h2412 #define mmPA_SC_ENHANCE … macro