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Searched refs:mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h5779 #define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
Ddcn_2_0_0_offset.h6717 #define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro