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Searched refs:mmMP1_SMN_C2PMSG_90 (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/smumgr/
Dsmu9_smumgr.c64 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
72 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
104 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc()
130 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc_with_parameter()
Dsmu10_smumgr.c54 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
59 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
85 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu10_send_msg_to_smc()
103 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu10_send_msg_to_smc_with_parameter()
Dvega20_smumgr.c73 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
78 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
110 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in vega20_send_msg_to_smc()
136 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in vega20_send_msg_to_smc_with_parameter()
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/
Dsmu_v12_0.c67 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu_v12_0_wait_for_response()
77 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO; in smu_v12_0_wait_for_response()
91 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu_v12_0_send_msg()
121 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu_v12_0_send_msg_with_param()
Dsmu_v11_0.c78 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu_v11_0_wait_for_response()
88 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO; in smu_v11_0_wait_for_response()
102 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu_v11_0_send_msg()
133 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu_v11_0_send_msg_with_param()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/mp/
Dmp_10_0_offset.h298 #define mmMP1_SMN_C2PMSG_90 macro
Dmp_12_0_0_offset.h298 #define mmMP1_SMN_C2PMSG_90 macro
Dmp_9_0_offset.h310 #define mmMP1_SMN_C2PMSG_90 0x029a macro
Dmp_11_0_offset.h300 #define mmMP1_SMN_C2PMSG_90 macro