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Searched refs:mmGDS_VMID0_SIZE (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c2033 adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); in gfx_v9_0_ngg_init()
2138 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), in gfx_v9_0_ngg_en()
2154 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); in gfx_v9_0_ngg_en()
2480 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); in gfx_v9_0_init_compute_vmid()
2498 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v9_0_init_gds_vmid()
4110 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, in gfx_v9_0_ring_emit_gds_switch()
4232 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); in gfx_v9_0_do_edc_gds_workarounds()
4257 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); in gfx_v9_0_do_edc_gds_workarounds()
Dgfx_v10_0.c1626 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); in gfx_v10_0_init_compute_vmid()
1644 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v10_0_init_gds_vmid()
3962 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, in gfx_v10_0_ring_emit_gds_switch()
Dgfx_v7_0.c95 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
5099 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()
Dgfx_v8_0.c178 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
7080 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v8_0_set_gds_init()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h2233 #define mmGDS_VMID0_SIZE 0x3301 macro
Dgfx_7_2_d.h2255 #define mmGDS_VMID0_SIZE 0x3301 macro
Dgfx_8_1_d.h2432 #define mmGDS_VMID0_SIZE 0x3301 macro
Dgfx_8_0_d.h2453 #define mmGDS_VMID0_SIZE 0x3301 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h3018 #define mmGDS_VMID0_SIZE macro
Dgc_9_1_offset.h3270 #define mmGDS_VMID0_SIZE macro
Dgc_9_2_1_offset.h3220 #define mmGDS_VMID0_SIZE macro
Dgc_10_1_0_offset.h5522 #define mmGDS_VMID0_SIZE macro