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Searched refs:mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h3939 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
Ddcn_1_0_offset.h3989 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
Ddcn_2_0_0_offset.h4877 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro