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Searched refs:mmDPG_WATERMARK_MASK_CONTROL (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_resource.c116 - mmDPG_WATERMARK_MASK_CONTROL),
122 - mmDPG_WATERMARK_MASK_CONTROL),
128 - mmDPG_WATERMARK_MASK_CONTROL),
134 - mmDPG_WATERMARK_MASK_CONTROL),
140 - mmDPG_WATERMARK_MASK_CONTROL),
146 - mmDPG_WATERMARK_MASK_CONTROL),
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c1054 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v8_0_program_watermarks()
1058 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v8_0_program_watermarks()
1063 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v8_0_program_watermarks()
1066 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v8_0_program_watermarks()
1071 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v8_0_program_watermarks()
Ddce_v10_0.c1119 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1121 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1128 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1134 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v10_0_program_watermarks()
Ddce_v11_0.c1145 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1147 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1154 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1160 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v11_0_program_watermarks()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h5180 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
Ddce_10_0_d.h6393 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
Ddce_11_0_d.h6516 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
Ddce_11_2_d.h7814 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro