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Searched refs:mmDC_HPD_INT_CONTROL (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Ddce_v10_0.c313 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity()
318 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_set_polarity()
348 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
350 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
3024 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3026 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3029 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3031 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3174 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack()
3176 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
Ddce_v11_0.c331 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_set_polarity()
336 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_set_polarity()
366 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
368 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
3150 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3152 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3155 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3157 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3300 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_int_ack()
3302 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_int_ack()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_11_0_d.h7281 #define mmDC_HPD_INT_CONTROL 0x1899 macro
Ddce_10_0_d.h7096 #define mmDC_HPD_INT_CONTROL 0x1899 macro
Ddce_11_2_d.h8663 #define mmDC_HPD_INT_CONTROL 0x1899 macro