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Searched refs:mmDB_RENDER_CONTROL (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h632 #define mmDB_RENDER_CONTROL 0xA000 macro
Dgfx_7_0_d.h612 #define mmDB_RENDER_CONTROL 0xa000 macro
Dgfx_7_2_d.h625 #define mmDB_RENDER_CONTROL 0xa000 macro
Dgfx_8_1_d.h697 #define mmDB_RENDER_CONTROL 0xa000 macro
Dgfx_8_0_d.h697 #define mmDB_RENDER_CONTROL 0xa000 macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2780 (void)RREG32(mmDB_RENDER_CONTROL); in gfx_v6_0_enable_gfx_cgpg()
Dgfx_v7_0.c3804 data = RREG32(mmDB_RENDER_CONTROL); in gfx_v7_0_enable_gfx_cgpg()
Dgfx_v9_0.c2895 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); in gfx_v9_0_enable_gfx_pipeline_powergating()
Dgfx_v8_0.c5396 RREG32(mmDB_RENDER_CONTROL); in cz_enable_gfx_pipeline_power_gating()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h3316 #define mmDB_RENDER_CONTROL … macro
Dgc_9_1_offset.h3568 #define mmDB_RENDER_CONTROL … macro
Dgc_9_2_1_offset.h3518 #define mmDB_RENDER_CONTROL … macro
Dgc_10_1_0_offset.h5706 #define mmDB_RENDER_CONTROL … macro