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Searched refs:mmD1VGA_CONTROL (Results 1 – 22 of 22) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_timing_generator.c398 offset = mmD2VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
401 offset = mmD3VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
404 offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
407 offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
410 offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
416 value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset); in dce120_timing_generator_disable_vga()
424 dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value); in dce120_timing_generator_disable_vga()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dcik.c902 d1vga_control = RREG32(mmD1VGA_CONTROL); in cik_read_disabled_bios()
912 WREG32(mmD1VGA_CONTROL, in cik_read_disabled_bios()
928 WREG32(mmD1VGA_CONTROL, d1vga_control); in cik_read_disabled_bios()
Dvi.c386 d1vga_control = RREG32(mmD1VGA_CONTROL); in vi_read_disabled_bios()
396 WREG32(mmD1VGA_CONTROL, in vi_read_disabled_bios()
412 WREG32(mmD1VGA_CONTROL, d1vga_control); in vi_read_disabled_bios()
Dgmc_v10_0.c608 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); in gmc_v10_0_get_vbios_fb_size()
Dgmc_v6_0.c822 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); in gmc_v6_0_get_vbios_fb_size()
Dgmc_v9_0.c1075 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); in gmc_v9_0_get_vbios_fb_size()
Dgmc_v7_0.c942 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); in gmc_v7_0_get_vbios_fb_size()
Dgmc_v8_0.c1060 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); in gmc_v8_0_get_vbios_fb_size()
Ddce_v8_0.c1724 mmD1VGA_CONTROL,
Ddce_v6_0.c1759 mmD1VGA_CONTROL,
Ddce_v10_0.c1795 mmD1VGA_CONTROL,
Ddce_v11_0.c1837 mmD1VGA_CONTROL,
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_timing_generator.c1807 addr = mmD1VGA_CONTROL; in dce110_timing_generator_disable_vga()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h1041 #define mmD1VGA_CONTROL 0x00CC macro
Ddce_8_0_d.h5144 #define mmD1VGA_CONTROL 0xcc macro
Ddce_11_0_d.h6104 #define mmD1VGA_CONTROL 0xcc macro
Ddce_10_0_d.h6027 #define mmD1VGA_CONTROL 0xcc macro
Ddce_11_2_d.h7778 #define mmD1VGA_CONTROL 0xcc macro
Ddce_12_0_offset.h574 #define mmD1VGA_CONTROL macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h112 #define mmD1VGA_CONTROL macro
Ddcn_1_0_offset.h408 #define mmD1VGA_CONTROL macro
Ddcn_2_0_0_offset.h52 #define mmD1VGA_CONTROL macro