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Searched refs:mmCP_RB1_RPTR_ADDR_HI (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h504 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 macro
Dgfx_7_0_d.h212 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 macro
Dgfx_7_2_d.h212 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 macro
Dgfx_8_1_d.h237 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 macro
Dgfx_8_0_d.h236 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2212 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v6_0_cp_compute_resume()
Dgfx_v10_0.c2842 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v10_0_cp_gfx_resume()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2427 #define mmCP_RB1_RPTR_ADDR_HI … macro
Dgc_9_1_offset.h2726 #define mmCP_RB1_RPTR_ADDR_HI … macro
Dgc_9_2_1_offset.h2664 #define mmCP_RB1_RPTR_ADDR_HI … macro
Dgc_10_1_0_offset.h4792 #define mmCP_RB1_RPTR_ADDR_HI … macro