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Searched refs:mmCP_RB1_CNTL (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h501 #define mmCP_RB1_CNTL 0x3061 macro
Dgfx_7_0_d.h203 #define mmCP_RB1_CNTL 0x3061 macro
Dgfx_7_2_d.h203 #define mmCP_RB1_CNTL 0x3061 macro
Dgfx_8_1_d.h228 #define mmCP_RB1_CNTL 0x3061 macro
Dgfx_8_0_d.h227 #define mmCP_RB1_CNTL 0x3061 macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2204 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
2206 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_compute_resume()
2215 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
Dgfx_v10_0.c2834 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
2851 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2423 #define mmCP_RB1_CNTL … macro
Dgc_9_1_offset.h2722 #define mmCP_RB1_CNTL … macro
Dgc_9_2_1_offset.h2660 #define mmCP_RB1_CNTL … macro
Dgc_10_1_0_offset.h4788 #define mmCP_RB1_CNTL … macro