Searched refs:mmCP_RB0_WPTR (Results 1 – 14 of 14) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v6_0.c | 2121 WREG32(mmCP_RB0_WPTR, ring->wptr); in gfx_v6_0_cp_gfx_resume()
2154 return RREG32(mmCP_RB0_WPTR); in gfx_v6_0_ring_get_wptr()
2167 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v6_0_ring_set_wptr_gfx()
2168 (void)RREG32(mmCP_RB0_WPTR); in gfx_v6_0_ring_set_wptr_gfx()
|
| D | gfx_v7_0.c | 2632 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v7_0_cp_gfx_resume()
2667 return RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
2674 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v7_0_ring_set_wptr_gfx()
2675 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
|
| D | gfx_v8_0.c | 4319 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v8_0_cp_gfx_resume()
6054 return RREG32(mmCP_RB0_WPTR); in gfx_v8_0_ring_get_wptr_gfx()
6066 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v8_0_ring_set_wptr_gfx()
6067 (void)RREG32(mmCP_RB0_WPTR); in gfx_v8_0_ring_set_wptr_gfx()
|
| D | gfx_v10_0.c | 2800 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
4332 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v10_0_ring_get_wptr_gfx()
4348 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_ring_set_wptr_gfx()
|
| D | gfx_v9_0.c | 3226 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_cp_gfx_resume()
4966 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v9_0_ring_get_wptr_gfx()
4982 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_ring_set_wptr_gfx()
|
| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 499 #define mmCP_RB0_WPTR 0x3045 macro
|
| D | gfx_7_0_d.h | 214 #define mmCP_RB0_WPTR 0x3045 macro
|
| D | gfx_7_2_d.h | 214 #define mmCP_RB0_WPTR 0x3045 macro
|
| D | gfx_8_1_d.h | 239 #define mmCP_RB0_WPTR 0x3045 macro
|
| D | gfx_8_0_d.h | 238 #define mmCP_RB0_WPTR 0x3045 macro
|
| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2393 #define mmCP_RB0_WPTR … macro
|
| D | gc_9_1_offset.h | 2692 #define mmCP_RB0_WPTR … macro
|
| D | gc_9_2_1_offset.h | 2630 #define mmCP_RB0_WPTR … macro
|
| D | gc_10_1_0_offset.h | 4758 #define mmCP_RB0_WPTR … macro
|
