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Searched refs:mmCP_RB0_BASE_HI (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h196 #define mmCP_RB0_BASE_HI 0x30b1 macro
Dgfx_7_2_d.h196 #define mmCP_RB0_BASE_HI 0x30b1 macro
Dgfx_8_1_d.h221 #define mmCP_RB0_BASE_HI 0x30b1 macro
Dgfx_8_0_d.h220 #define mmCP_RB0_BASE_HI 0x30b1 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2560 #define mmCP_RB0_BASE_HI … macro
Dgc_9_1_offset.h2852 #define mmCP_RB0_BASE_HI … macro
Dgc_9_2_1_offset.h2786 #define mmCP_RB0_BASE_HI … macro
Dgc_10_1_0_offset.h4920 #define mmCP_RB0_BASE_HI … macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c2647 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v7_0_cp_gfx_resume()
Dgfx_v10_0.c2820 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v10_0_cp_gfx_resume()
Dgfx_v9_0.c3243 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v9_0_cp_gfx_resume()
Dgfx_v8_0.c4334 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v8_0_cp_gfx_resume()