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Searched refs:mmCP_PQ_WPTR_POLL_CNTL1 (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/inc/
Dpolaris10_pwrvirus.h1785 { 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 },
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v9.c337 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), in kgd_gfx_v9_hqd_load()
Damdgpu_amdkfd_gfx_v10.c437 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), in kgd_hqd_load()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h263 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
Dgfx_7_2_d.h265 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
Dgfx_8_1_d.h296 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
Dgfx_8_0_d.h296 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2472 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
Dgc_9_1_offset.h2768 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
Dgc_9_2_1_offset.h2704 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
Dgc_10_1_0_offset.h4834 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro