| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | mxgpu_vi.c | 91 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
222 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
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| D | si.c | 545 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
642 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
742 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
822 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
899 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
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| D | gfx_v6_0.c | 2618 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2621 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
2642 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2645 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
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| D | gfx_v8_0.c | 304 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
467 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
674 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
707 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5520 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v8_0_get_clockgating_state()
5718 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v8_0_update_medium_grain_clock_gating()
5721 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v8_0_update_medium_grain_clock_gating()
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| D | gfx_v7_0.c | 3623 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3626 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
3676 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3679 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
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| D | gfx_v10_0.c | 4072 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
4075 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
4096 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
4099 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
4304 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_get_clockgating_state()
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| D | gfx_v9_0.c | 4651 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4654 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4680 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4683 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4936 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_get_clockgating_state()
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 455 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| D | gfx_7_0_d.h | 255 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| D | gfx_7_2_d.h | 257 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| D | gfx_8_1_d.h | 289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| D | gfx_8_0_d.h | 289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2455 #define mmCP_MEM_SLP_CNTL … macro
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| D | gc_9_1_offset.h | 2754 #define mmCP_MEM_SLP_CNTL … macro
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| D | gc_9_2_1_offset.h | 2692 #define mmCP_MEM_SLP_CNTL … macro
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| D | gc_10_1_0_offset.h | 4818 #define mmCP_MEM_SLP_CNTL … macro
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