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Searched refs:mmCP_MEC_ME1_UCODE_ADDR (Results 1 – 15 of 15) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dpsp_v10_0.c277 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); in psp_v10_0_sram_map()
Dpsp_v12_0.c431 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); in psp_v12_0_sram_map()
Dpsp_v3_1.c509 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); in psp_v3_1_sram_map()
Dpsp_v11_0.c594 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); in psp_v11_0_sram_map()
Dgfx_v7_0.c2745 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
2748 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
Dgfx_v10_0.c2947 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v10_0_cp_compute_load_microcode()
2953 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v10_0_cp_compute_load_microcode()
Dgfx_v9_0.c3316 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, in gfx_v9_0_cp_compute_load_microcode()
3322 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, in gfx_v9_0_cp_compute_load_microcode()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h250 #define mmCP_MEC_ME1_UCODE_ADDR 0x305c macro
Dgfx_7_2_d.h252 #define mmCP_MEC_ME1_UCODE_ADDR 0x305c macro
Dgfx_8_1_d.h282 #define mmCP_MEC_ME1_UCODE_ADDR 0xf81a macro
Dgfx_8_0_d.h281 #define mmCP_MEC_ME1_UCODE_ADDR 0xf81a macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6716 #define mmCP_MEC_ME1_UCODE_ADDR macro
Dgc_9_1_offset.h6962 #define mmCP_MEC_ME1_UCODE_ADDR macro
Dgc_9_2_1_offset.h6990 #define mmCP_MEC_ME1_UCODE_ADDR macro
Dgc_10_1_0_offset.h10224 #define mmCP_MEC_ME1_UCODE_ADDR macro