Home
last modified time | relevance | path

Searched refs:mmCP_MEC1_F32_INT_DIS (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_1_d.h286 #define mmCP_MEC1_F32_INT_DIS 0x30bd macro
Dgfx_8_0_d.h285 #define mmCP_MEC1_F32_INT_DIS 0x30bd macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2584 #define mmCP_MEC1_F32_INT_DIS macro
Dgc_9_1_offset.h2876 #define mmCP_MEC1_F32_INT_DIS macro
Dgc_9_2_1_offset.h2810 #define mmCP_MEC1_F32_INT_DIS macro
Dgc_10_1_0_offset.h4938 #define mmCP_MEC1_F32_INT_DIS macro