Home
last modified time | relevance | path

Searched refs:mmCP_INT_CNTL_RING0 (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2260 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_enable_gui_idle_interrupt()
2270 WREG32(mmCP_INT_CNTL_RING0, tmp); in gfx_v6_0_enable_gui_idle_interrupt()
3243 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3245 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3248 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3250 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3306 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_priv_reg_fault_state()
3308 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state()
3311 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_priv_reg_fault_state()
3313 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state()
[all …]
Dgfx_v7_0.c3170 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_enable_gui_idle_interrupt()
3178 WREG32(mmCP_INT_CNTL_RING0, tmp); in gfx_v7_0_enable_gui_idle_interrupt()
4709 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4711 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4714 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4716 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4783 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4785 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state()
4788 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4790 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state()
[all …]
Dgfx_v10_0.c1774 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v10_0_enable_gui_idle_interrupt()
1785 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); in gfx_v10_0_enable_gui_idle_interrupt()
4823 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v10_0_set_gfx_eop_interrupt_state()
Dgfx_v9_0.c2592 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v9_0_enable_gui_idle_interrupt()
2599 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); in gfx_v9_0_enable_gui_idle_interrupt()
Dgfx_v8_0.c3908 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v8_0_enable_gui_idle_interrupt()
3915 WREG32(mmCP_INT_CNTL_RING0, tmp); in gfx_v8_0_enable_gui_idle_interrupt()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h438 #define mmCP_INT_CNTL_RING0 0x306A macro
Dgfx_7_0_d.h222 #define mmCP_INT_CNTL_RING0 0x306a macro
Dgfx_7_2_d.h222 #define mmCP_INT_CNTL_RING0 0x306a macro
Dgfx_8_1_d.h247 #define mmCP_INT_CNTL_RING0 0x306a macro
Dgfx_8_0_d.h246 #define mmCP_INT_CNTL_RING0 0x306a macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2441 #define mmCP_INT_CNTL_RING0 … macro
Dgc_9_1_offset.h2740 #define mmCP_INT_CNTL_RING0 … macro
Dgc_9_2_1_offset.h2678 #define mmCP_INT_CNTL_RING0 … macro
Dgc_10_1_0_offset.h4804 #define mmCP_INT_CNTL_RING0 … macro