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Searched refs:mmCP_HQD_PQ_WPTR_POLL_ADDR_HI (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/inc/
Dpolaris10_pwrvirus.h1510 { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
1520 { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
1530 { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
1540 { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v9.c335 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), in kgd_gfx_v9_hqd_load()
Damdgpu_amdkfd_gfx_v10.c434 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), in kgd_hqd_load()
Dgfx_v10_0.c3420 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v10_0_kiq_init_register()
Dgfx_v9_0.c3623 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v9_0_kiq_init_register()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h581 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 macro
Dgfx_7_2_d.h594 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 macro
Dgfx_8_1_d.h644 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 macro
Dgfx_8_0_d.h644 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2820 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI macro
Dgc_9_1_offset.h3070 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI macro
Dgc_9_2_1_offset.h3026 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI macro
Dgc_10_1_0_offset.h5308 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI macro