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Searched refs:mmCP_HQD_IB_CONTROL (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h588 #define mmCP_HQD_IB_CONTROL 0x325a macro
Dgfx_7_2_d.h601 #define mmCP_HQD_IB_CONTROL 0x325a macro
Dgfx_8_1_d.h651 #define mmCP_HQD_IB_CONTROL 0x325a macro
Dgfx_8_0_d.h651 #define mmCP_HQD_IB_CONTROL 0x325a macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c3544 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); in gfx_v9_0_mqd_init()
3687 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); in gfx_v9_0_kiq_fini_register()
Dgfx_v7_0.c3027 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); in gfx_v7_0_mqd_init()
Dgfx_v10_0.c3340 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); in gfx_v10_0_compute_mqd_init()
Dgfx_v8_0.c4564 tmp = RREG32(mmCP_HQD_IB_CONTROL); in gfx_v8_0_mqd_init()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2832 #define mmCP_HQD_IB_CONTROL … macro
Dgc_9_1_offset.h3082 #define mmCP_HQD_IB_CONTROL … macro
Dgc_9_2_1_offset.h3038 #define mmCP_HQD_IB_CONTROL … macro
Dgc_10_1_0_offset.h5320 #define mmCP_HQD_IB_CONTROL … macro