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Searched refs:mmCP_HQD_DEQUEUE_REQUEST (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v7.c609 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
624 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
Damdgpu_amdkfd_gfx_v8.c605 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
620 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
Damdgpu_amdkfd_gfx_v10.c709 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
725 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); in kgd_hqd_destroy()
Damdgpu_amdkfd_gfx_v9.c563 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); in kgd_gfx_v9_hqd_destroy()
Dgfx_v9_0.c3578 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_0_kiq_init_register()
3584 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v9_0_kiq_init_register()
3667 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_0_kiq_fini_register()
3682 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v9_0_kiq_fini_register()
Dgfx_v7_0.c2910 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v7_0_mqd_deactivate()
2920 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v7_0_mqd_deactivate()
Dgfx_v10_0.c3375 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v10_0_kiq_init_register()
3381 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v10_0_kiq_init_register()
Dgfx_v8_0.c4450 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v8_0_deactivate_hqd()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h591 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
Dgfx_7_2_d.h604 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
Dgfx_8_1_d.h654 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
Dgfx_8_0_d.h654 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2838 #define mmCP_HQD_DEQUEUE_REQUEST macro
Dgc_9_1_offset.h3088 #define mmCP_HQD_DEQUEUE_REQUEST macro
Dgc_9_2_1_offset.h3044 #define mmCP_HQD_DEQUEUE_REQUEST macro
Dgc_10_1_0_offset.h5326 #define mmCP_HQD_DEQUEUE_REQUEST macro