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Searched refs:mmCP_CPC_IC_BASE_HI (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/inc/
Dpolaris10_pwrvirus.h59 { 0x000000b4, mmCP_CPC_IC_BASE_HI },
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/smumgr/
Dsmu8_smumgr.c214 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data); in smu8_load_mec_firmware()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_1_d.h347 #define mmCP_CPC_IC_BASE_HI 0x30ba macro
Dgfx_8_0_d.h347 #define mmCP_CPC_IC_BASE_HI 0x30ba macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c2354 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
2943 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, in gfx_v10_0_cp_compute_load_microcode()
Dgfx_v9_0.c3312 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, in gfx_v9_0_cp_compute_load_microcode()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2578 #define mmCP_CPC_IC_BASE_HI macro
Dgc_9_1_offset.h2870 #define mmCP_CPC_IC_BASE_HI macro
Dgc_9_2_1_offset.h2804 #define mmCP_CPC_IC_BASE_HI macro
Dgc_10_1_0_offset.h10258 #define mmCP_CPC_IC_BASE_HI macro