Searched refs:mmCP_CPC_IC_BASE_CNTL (Results 1 – 9 of 9) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | smu8_smumgr.c | 200 mmCP_CPC_IC_BASE_CNTL); in smu8_load_mec_firmware()
206 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp); in smu8_load_mec_firmware()
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_8_1_d.h | 348 #define mmCP_CPC_IC_BASE_CNTL 0x30bb macro
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| D | gfx_8_0_d.h | 348 #define mmCP_CPC_IC_BASE_CNTL 0x30bb macro
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| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v10_0.c | 2935 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); in gfx_v10_0_cp_compute_load_microcode()
2939 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); in gfx_v10_0_cp_compute_load_microcode()
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| D | gfx_v9_0.c | 3308 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); in gfx_v9_0_cp_compute_load_microcode()
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2580 #define mmCP_CPC_IC_BASE_CNTL … macro
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| D | gc_9_1_offset.h | 2872 #define mmCP_CPC_IC_BASE_CNTL … macro
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| D | gc_9_2_1_offset.h | 2806 #define mmCP_CPC_IC_BASE_CNTL … macro
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| D | gc_10_1_0_offset.h | 10260 #define mmCP_CPC_IC_BASE_CNTL … macro
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