Searched refs:mmCPC_INT_CNTL (Results 1 – 13 of 13) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_amdkfd_gfx_v7.c | 298 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
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| D | amdgpu_amdkfd_gfx_v8.c | 255 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
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| D | amdgpu_amdkfd_gfx_v9.c | 220 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), in kgd_gfx_v9_init_interrupts()
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| D | amdgpu_amdkfd_gfx_v10.c | 300 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), in kgd_init_interrupts()
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| D | gfx_v10_0.c | 5091 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()
5094 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); in gfx_v10_0_kiq_set_interrupt_state()
5101 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()
5104 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); in gfx_v10_0_kiq_set_interrupt_state()
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_7_0_d.h | 264 #define mmCPC_INT_CNTL 0x30b4 macro
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| D | gfx_7_2_d.h | 266 #define mmCPC_INT_CNTL 0x30b4 macro
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| D | gfx_8_1_d.h | 297 #define mmCPC_INT_CNTL 0x30b4 macro
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| D | gfx_8_0_d.h | 297 #define mmCPC_INT_CNTL 0x30b4 macro
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2566 #define mmCPC_INT_CNTL … macro
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| D | gc_9_1_offset.h | 2858 #define mmCPC_INT_CNTL … macro
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| D | gc_9_2_1_offset.h | 2792 #define mmCPC_INT_CNTL … macro
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| D | gc_10_1_0_offset.h | 4926 #define mmCPC_INT_CNTL … macro
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